The present invention relates to an isolation technology for semiconductor devices. A variety of methods and structures have been used to isolate areas on semiconductor devices. One conventional technology is based on localized oxidation of silicon (LOCOS), shown in FIG. 1. In FIG. 1, on the silicon substrate 102 is a field oxide 104 that acts to isolate an active area of the semiconductor device; the field oxide is contiguous with the gate oxide 110 on the active region of the silicon substrate. The active area in this illustration includes a layer of silicon nitride 106. The field oxide encroaches on the active area in the shape of a bird's beak 108, before narrowing into the gate oxide. This large encroachment distorts the active region, and interferes with the submicron lithography necessary to construct elements in the active region.
Another widely used isolation technique is silicon trench isolation (STI), shown in FIG. 2. The field oxide 104 does not have the shape of a bird's beak where it narrows into the gate oxide 110 on the silicon substrate 102. FIGS. 3(a)-3(e) illustrate the step used to prepare the structure shown in FIG. 2. In FIG. 3(a) thermal oxidizing forms a thermal oxide layer 111 on the silicon substrate 102, followed by depositing a silicon nitride layer 106 using low pressure chemical vapor deposition (LPCVD). In FIG. 3(b) a photoresist layer 112 is applied, and patterned using a mask. Etching of those portions of the silicon nitride, thermal oxide and silicon substrate not covered by the photoresist layer, in a single operation, opens a trench 114.
In FIG. 3(c) the photoresist layer is first stripped, and the substrate is cleaned. A thin oxide layer 118 is then grown by dry oxidation of the exposed portions of the silicon substrate. An oxide layer 116 is then deposited into the trench and across the surface of the structure by chemical vapor deposition (CVD). In FIG. 3(d) chemical-mechanical polishing (CMP) planarizes the surface, leaving the oxide layer 116 only in the trench. In FIG. 3(e) the silicon nitride and thermal oxide layers are removed, and a gate oxide layer 110 is grown on the silicon substrate.
After forming the field oxide, additional processing is used to produce semiconductor devices on the substrate. These subsequent processes include heating cycles, for example during CVD oxide desification or drive-in for preparing doped regions. Since there is mismatch between the thermal expansion of the substrate and the field oxide, stress is induced at the interface between them during heating. If the temperature is sufficiently high during heating such that the yield point of the substrate is reduced to a value comparable to the strain induced by the heating, then the substrate will relax at the high temperature and lock the strain in at room temperature. The locked in strain might cause dislocations and a strained surface of silicon at the interface, producing high leakage rates during operation of devices. For example, the expansion coefficient between silicon dioxide and silicon at 800° C. is about 0.26%, which is beyond the yield point of silicon at 800° C., and therefore plastic deformation of the silicon will take place at the interface; upon cooling to room temperature strain will be present at the interface.
U.S. Pat. No. 4,851,662 to Park et al. discloses a method of forming a isolation trench in which a nitride liner formed in a trench is protected during subsequent plasma processing. After forming the nitride liner, a high temperature oxide layer is formed on the nitride liner using a first process. Then, upon forming the high temperature oxide layer, plasma processing is performed on the surface of the high temperature oxide layer. After the plasma processing, a trench fill dielectric layer to fill the trench is formed on the high temperature oxide layer using a second process. Park et al. forms two types of layers using two process steps in addition to plasma processing in order to fill the trench upon depositing the nitride liner.